Field of the Invention: The present invention relates generally to the design and testing of integrated circuit devices. Specifically, the present invention relates to the electrical characterization of integrated circuit device packages at high operating frequencies and, in particular, to apparatus and methods for measuring parasitic capacitance and inductance of one or more I/O leads of an integrated circuit device package using a network analyzer.
State of the Art: Designers of integrated circuit devices are facing increasingly difficult challenges as a result of the current trend toward integrated circuit devices exhibiting small overall package dimensions and having a large number of leads, yet being capable of operating at high frequencies. Such an integrated circuit device may include a complex array of closely spaced electrical leads adapted for establishing electrical communication with a semiconductor die, each lead having one end electrically connected to the semiconductor die and an opposing end adapted for electrical connection to an external device, such as a printed circuit board. Presently, a wide variety of integrated circuit package types and configurations are commercially available, including, for example, Ball Grid Array (BGA) packages, Thin Small Outline Packages (TSOPs), as well as other package types. It is a continuing goal of integrated circuit package designers to adapt these package configurations to fit within ever-decreasing volumes, to include a large number of electrical leads, and to operate at high frequencies in order to meet the demand for such devices.
An exemplary embodiment of a conventional BGA package 100 is shown in FIGS. 1 and 2. The conventional BGA package 100 may be a memory device, such as a DRAM chip, a processor, or any other integrated circuit device known in the art. The conventional BGA package 100 includes a semiconductor die 110 secured to a die-attach pad 112 formed on an upper surface 106 of a substrate 105, which may also be termed an interposer. The BGA package 100 also includes a plurality of electrical leads 130 adapted to provide electrical communication between the semiconductor die 110 and one or more external devices (not shown). The semiconductor die 110 and at least a portion of each electrical lead 130 may be encased by an encapsulant material 120 or, alternatively, the conventional BGA package 100 may have no encapsulant material 120, depending upon the particular package construction and intended use.
Each of the electrical leads 130 includes an external ball lead 132 configured for electrical connection to an external device. The ball lead 132 may be secured to a conductive pad 133 formed on a lower surface 107 of the substrate 105. Each electrical lead 130 further comprises a conductive via 134 extending from the conductive pad 133 and through the substrate 105 to a conductive trace 136. The conductive trace 136 is formed on the upper surface 106 of the substrate 105 and provides an electrical path from the conductive via 134 to a bond end 137 located proximate the semiconductor die 110. A bond wire 138 attached to the bond end 137 of the conductive trace 136 and extending to the semiconductor die 110, where the bond wire 138 is attached to a bond pad thereon, electrically connects the electrical lead 130 to the semiconductor die 110. At least the bond wire 138 and conductive trace 136 of each electrical lead 130 may be encased by the encapsulant material 120.
The conventional BGA package 100 may include a plurality of the ball leads 132 arranged, for example, in an array or arrays of mutually adjacent rows and columns. Referring to FIG. 1, the ball leads 132 may be arranged in two arrays 150, 160, each array 150, 160 disposed between an edge of the semiconductor die 110 and a peripheral edge of the substrate 105. Each array 150, 160 comprises three columns 151, 152, 153, 161, 162, 163, respectively, of ball leads 132. The arrangement of ball leads 132 is typically referred to as the “pin-out” or the “footprint” of the BGA package 100. The pin-out of the BGA package 100 may, by way of example, comprise outer and inner columns 151, 161, 153, 163, respectively, of ball leads 132 adapted to provide input and output of electrical signals to and from the semiconductor die 110, such ball leads 132 being referred to herein as “I/O leads.” The pin-out may further comprise center columns 152, 162 of ball leads 132 adapted to provide a power signal to the semiconductor die 110 (a “VCC lead”), to provide a ground potential for the semiconductor die 110 (a “VSS lead”), or to provide a reference voltage to the semiconductor die 110 (a “VREF lead”). However, those of ordinary skill in the art will understand that the particular pin-out of an integrated circuit device may vary depending upon the application and that the pin-out may be of any suitable configuration.
An exemplary embodiment of a conventional TSOP 200 is shown in FIGS. 3 and 4. The conventional TSOP 200 may be a memory device, such as a DRAM chip, a processor, or any other integrated circuit device known in the art. The conventional TSOP 200 includes a semiconductor die 210 secured to a die-attach pad 212. The TSOP 200 further includes a plurality of electrical leads 230 adapted to provide electrical communication between the semiconductor die 210 and one or more external devices (not shown). The semiconductor die 210 and at least a portion of each electrical lead 230 are encased by an encapsulant material 220.
Each of the electrical leads 230 includes an external portion 232 configured for electrical connection to an external device. Each electrical lead 230 also includes an internal portion 234 extending from the external portion 232 to a bond end 235 located proximate the semiconductor die 210. A transversely extending bus bar or bars 239 may extend between two or more electrical leads 230. A bond wire 238 electrically connects the bond end 235 of the internal portion 234 to a bond pad on the semiconductor die 210 to establish electrical communication therebetween. Bond wires 238 may also extend between the transverse bus bar or bars 239 and one or more bond pads on the semiconductor die 210. At least the internal portion 234 and bond wire 238 of each electrical lead 230 are encased by the encapsulant material 220.
The external portion 232 and internal portion 234 of each electrical lead 230 typically comprise a single piece of material commonly referred to as a lead finger. Further, the lead fingers (external and internal portions 232, 234), bus bar or bars 239, and die-attach pad 212 typically comprise a structure usually referred to as a lead frame. Integrated circuit packages utilizing lead frame construction are well known in the art. It will be appreciated by those of ordinary skill in the art that the conventional TSOP 200 may include a lead frame of any configuration known in the art and, further, that the internal portion 234 may extend over and directly attach to the semiconductor die 210, such a lead frame being commonly referred to as a Leads-Over-Chip (LOC) configuration.
The external portions 232 of the electrical leads 230 extend from one or more edges of the TSOP 200 and are arranged in a row therealong. For example, as shown in FIG. 3, the TSOP 200 may include a row 250 of electrical leads 230 extending from an edge of the TSOP 200 and another row 260 of electrical leads 230 extending from an opposing edge of the TSOP 200. The arrangement of the external portions 232 of the electrical leads 230 comprises the pin-out or footprint of the TSOP 200. An electrical lead 230 may be an I/O lead, a VCC lead, a VSS lead, or a VREF lead, as noted above, and the particular configuration of the pin-out will vary depending upon the application.
For both the conventional BGA package 100 and the conventional TSOP 200, as well as for other conventional integrated circuit package types, the spacing between the electrical leads 130, 230—especially between adjacent conductive traces 136 and between adjacent internal portions 234 thereof, respectively—is becoming increasingly smaller to accommodate smaller overall package sizes and greater numbers of electrical leads 130, 230, as was suggested above. This close spacing between adjacent electrical leads 130, 230 in the conventional BGA and TSOP packages 100, 200, respectively, in conjunction with increasingly higher operating frequencies for newer integrated circuit devices, may lead to mutual coupling between adjacent electrical leads 130, 230, which may compromise signal integrity during operation of the integrated circuit package.
Mutual coupling between adjacent electrical leads of an integrated circuit device, especially at high frequencies, presents a difficult problem for integrated circuit package designers. The mutual coupling between adjacent electrical leads of an integrated circuit package, as well as between an electrical lead and other components of the integrated circuit package, may include mutual capacitance and mutual inductance, both of which are frequency dependent. Thus, as newer integrated circuit packages are being designed to operate in relatively higher frequency ranges—e.g., in the range of 100 MHz to 400 MHz and higher—the deleterious effects of mutual coupling on signal integrity become increasingly significant, and package designers must have tools available to quantify such effects. Mutual capacitances and mutual inductances within an integrated circuit package are commonly referred to as parasitic capacitance and parasitic inductance, or simply parasitics.
Shown in FIG. 5 is an electrical model of two adjacent electrical leads 130a, 130b in the conventional BGA package 100. The electrical lead 130a includes a resistance 801a, an inductance 802a, and a capacitance 803a. Similarly, the electrical lead 130b includes a resistance 801b, an inductance 802b, and a capacitance 803b. The electrical model depicted in FIG. 5 is commonly referred to as a “lumped” model.
Referring to FIG. 5, the resistance 801a comprises the individual resistances of the bond wire 138, the conductive trace 136, the conductive via 134, the conductive pad 133, and the ball lead 132 of electrical lead 130a. The inductance 802a comprises the individual inductances of the bond wire 138, the conductive trace 136, the conductive via 134, the conductive pad 133, and the ball lead 132 of electrical lead 130a, and further includes mutual inductances generated between the electrical lead 130a and the adjacent electrical lead 130b, as well as between the electrical lead 130a and other components of the BGA package 100. The capacitance 803a comprises the individual capacitances of the bond wire 138, the conductive trace 136, the conductive via 134, the conductive pad 133, and the ball lead 132 of electrical lead 130a, and further includes mutual capacitances generated between the electrical lead 130a and the adjacent electrical lead 130b, as well as between the electrical lead 130a and other components of the BGA package 100. The mutual inductances and mutual capacitances are, at least in part, dependent upon the configuration of, and the distance between, the adjacent electrical leads 130a, 130b and upon the magnitude and frequency of the electrical signals propagating through each of the adjacent electrical leads 130a, 130b, as well as through other surrounding electrical leads 130 and other components of the BGA package 100.
Similarly, the resistance 801b comprises the individual resistances of the bond wire 138, the conductive trace 136, the conductive via 134, the conductive pad 133, and the ball lead 132 of the electrical lead 130b. The inductance 802b comprises the individual inductances of the bond wire 138, the conductive trace 136, the conductive via 134, the conductive pad 133, and the ball lead 132 of electrical lead 130b, and further includes mutual inductances generated between the electrical lead 130b and the adjacent electrical lead 130a, as well as between the electrical lead 130b and other components of the BGA package 100. The capacitance 803b comprises the individual capacitances of the bond wire 138, the conductive trace 136, the conductive via 134, the conductive pad 133, and the ball lead 132 of electrical lead 130b, and further includes mutual capacitances generated between the electrical lead 130b and the adjacent electrical lead 130a, as well as between the electrical lead 130b and other components of the BGA package 100. Again, the mutual inductances and mutual capacitances are, at least in part, dependent upon the configuration of, and the distance between, the adjacent electrical leads 130b, 130a and upon the magnitude and frequency of the electrical signals propagating through each of the adjacent electrical leads 130b, 130a, as well as through other surrounding electrical leads 130 and other components of the BGA package 100.
Shown in FIG. 6 is an electrical model of two adjacent electrical leads 230a, 230b in the conventional TSOP 200. The electrical lead 230a includes a resistance 901a, an inductance 902a, and a capacitance 903a. Similarly, the electrical lead 230b includes a resistance 901b, an inductance 902b, and a capacitance 903b. The electrical model depicted in FIG. 6 is commonly referred to as a “lumped” model, as noted above.
Referring to FIG. 6, the resistance 901a comprises the individual resistances of the bond wire 238, the internal portion 234, and the external portion 232 of electrical lead 230a. The inductance 902a comprises the individual inductances of the bond wire 238, the internal portion 234, and the external portion 232 of electrical lead 230a, and further includes mutual inductances generated between the electrical lead 230a and the adjacent electrical lead 230b, as well as between the electrical lead 230a and other components of the TSOP 200. The capacitance 903a comprises the individual capacitances of the bond wire 238, the internal portion 234, and the external portion 232 of electrical lead 230a, and further includes mutual capacitances generated between the electrical lead 230a and the adjacent electrical lead 230b, as well as between the electrical lead 230a and other components of the TSOP 200. The mutual inductances and mutual capacitances are, at least in part, dependent upon the configuration of, and the distance between, the adjacent electrical leads 230a, 230b and upon the magnitude and frequency of the electrical signals propagating through each of the adjacent electrical leads 230a, 230b, as well as through other surrounding electrical leads 230 and other components of the TSOP 200.
Similarly, the resistance 901b comprises the individual resistances of the bond wire 238, the internal portion 234, and the external portion 232 of electrical lead 230b. The inductance 902b comprises the individual inductances of the bond wire 238, the internal portion 234, and the external portion 232 of electrical lead 230b, and further includes mutual inductances generated between the electrical lead 230b and the adjacent electrical lead 230a, as well as between the electrical lead 230b and other components of the TSOP 200. The capacitance 903b comprises the individual capacitances of the bond wire 238, the internal portion 234, and the external portion 232 of electrical lead 230b, and further includes mutual capacitances generated between the electrical lead 230b and the adjacent electrical lead 230a, as well as between the electrical lead 230b and other components of the TSOP 200. Again, the mutual inductances and mutual capacitances are, at least in part, dependent upon the configuration of, and the distance between, the adjacent electrical leads 230b, 230a and upon the magnitude and frequency of the electrical signals propagating through each of the adjacent electrical leads 230b, 230a, as well as through other surrounding electrical leads 230 and other components of the TSOP 200.
Mutual coupling between the electrical leads of an integrated circuit package, and between an electrical lead and other components of the integrated circuit package, are often difficult for the integrated circuit package designer to accurately model, either by direct computation methods or by using computer-based simulation techniques. However, integrated circuit package characterization is a critical, if not essential, aspect of the integrated circuit package design process. Package designers must be able to verify that a proposed package configuration will behave electrically as intended, and that parasitic capacitances and inductances will not compromise signal integrity. Thus, in addition to modeling the electrical behavior of an integrated circuit package design using direct computation methods or computer-based simulation, it is often desirable to directly measure certain electrical characteristics—such as parasitic capacitance and inductance—of an integrated circuit package design using measuring instruments in order to validate the electrical model.
One type of conventional measuring instrument routinely used to measure inductance and capacitance is what is often referred to as an RLC meter. There are numerous types of RLC meters commercially available from a number of manufacturers; however, most conventional RLC meters suffer from the same limitation—i.e., the inability to accurately measure inductance and capacitance at high frequencies. Conventional RLC meters have an upper frequency limit of approximately 13 MHz. As noted above, new integrated circuit packages are being designed to operate in frequency ranges of 100 MHz to 400 MHz and higher, requiring that package characterization be performed at frequencies up to 3 GHz and higher in order to obtain accurate data. Thus, for newer integrated circuit packages designed to operate at relatively high frequencies, conventional RLC meters will not provide an accurate indication of the potential for mutual coupling in an integrated circuit package during operation.
One type of measuring instrument that has demonstrated an ability to provide relatively accurate measurements of parasitic capacitances and inductances in integrated circuit packages is a vector network analyzer (VNA), which may simply be referred to as a network analyzer. Generally, a network analyzer is a two-port measuring device having the ability to send a test signal or signals to a device under test (DUT) from one port and to receive a reflected signal or signals from the DUT at the same port. The ratio of the reflected signal to the original test signal (or a ratio of the average of the reflected signals to the original test signal if multiple test signals are sent) may be used to calculate what is commonly referred to as the S11 parameter or the S22 parameter. Use of a network analyzer to measure a reflected signal or signals is often referred to as using the network analyzer in the “S11 mode.” Alternatively, the network analyzer may send a test signal or signals to a DUT from one port and receive a signal or signals transmitted through the DUT at the other port. The ratio of the transmitted signal to the original test signal (or a ratio of the average of the transmitted signals to the original test signal if multiple test signals are sent) may be used to calculate what is commonly referred to as the S12 parameter or the S21 parameter. Use of a network analyzer to measure the transmitted signal or signals is often referred to as using the network analyzer in the “S12 mode.” Each port of the network analyzer is adapted to both send and receive high frequency electrical signals in the 3 GHz range as well as higher frequencies. The S11, S12, S21, and S22 parameters are often referred to as “scatter” parameters.
Although traditionally used by radio frequency and transmission line designers, a network analyzer may be used to characterize integrated circuit packages. In the S11 mode, a network analyzer can be configured to send a high frequency test signal or signals to a selected lead or leads of an integrated circuit package and to measure the signal or signals reflected back from the integrated circuit package. Contact between a port of the network analyzer and a lead or leads of the integrated circuit package can be established by a test probe, such as a coaxial probe, electrically connected to the port of the network analyzer. The power exhibited by the reflected signal (or the average power of multiple reflected signals if more than one test signal is sent) received from the integrated circuit package is directly related to the impedance of the integrated circuit package and to the impedance of the network analyzer and test probe. By appropriate test setup and calibration, the impedance of the network analyzer and test probe can be removed from the measured data, such that the impedance indicated by the network analyzer is substantially that of the integrated circuit package. Also, the network analyzer may be configured to provide capacitance and inductance data for the integrated circuit package in a Smith chart format (see FIGS. 16 and 17).
Thus, a network analyzer may be used to measure the parasitic capacitances and inductances at high frequencies of one or more electrical leads of an integrated circuit package. However, though it is known in the art to use network analyzers to measure high frequency parasitics in an integrated circuit package, conventional apparatus and methods for acquiring such data utilize complex and expensive test fixtures and methods. For the integrated circuit package designer, who may need an indication of the potential for mutual coupling in a proposed package design at an intermediate phase of the design process, a relatively simple, fast, and low-cost method for measuring parasitic capacitances and inductances is preferred.
Therefore, a need exists in the art for apparatus and methods for determining the susceptibility of a proposed integrated circuit package design to mutual coupling between electrical leads, or between an electrical lead and other components of the integrated circuit device package, using a network analyzer. Such apparatus and methods must provide a relatively simple and low-cost approach to integrated circuit package characterization.